Display PCI devices (QNX)
show_pci [-v]
- -v
- Verbose.
The show_pci command is used for diagnostic purposes to
provide information on PCI Local Bus configuration. This information
can be used to troubleshoot misconfigurations and to assist in
finding out correct options to specify to device drivers.
Detailing the significance of all the information returned by
show_pci is beyond the scope of this document. However,
here are the meanings of some of the common fields returned
by show_pci:
- PCI version
- This is the version of the PCI bus being used in the machine.
- Vendor ID
- A 16-bit number indicating the manufacturer of the device.
Vendor IDs are allocated by the PCI Special Interest Group.
The show_pci utility is aware of some of the more common
ones. For those that it knows, it will display the manufacturer
name after the hexadecimal number. (e.g. 8086h, INTEL CORPORATION)
- Device ID
- A 16-bit number identifying the particular device. The device
ID is allocated by the device manufacturer (see Vendor ID).
- PCI index
- The PCI index corresponds to the Nth occurrence of a device. For
example if there are two identical devices in a machine the BIOS
will assign them a PCI index of 0 and 1.
- Class Code
- The class code register identifies the general function of
the device. The show_pci command will display
the meaning of known classes after the hexadecimal class
number. e.g. 10180h Mass Storage (IDE) ProgIF=128
- Revision ID
- An 8-bit number which identifies a device-specific revision
number, chosen by the device manufacturer (see Vendor ID).
- Bus number
- This is a number in the range 0 to 255 that uniquely selects a PCI bus.
- Device number
- This is a number in the range 0 to 31 that uniquely selects a device on
a PCI bus.
- Function num
- This is a number in the range 0 to 7 that uniquely selects a function within
a multi-function PCI device.
- Status Reg
- The contents (in hex) of the device's status register.
| Bit |
Meaning
|
| 0-4 |
Reserved.
|
| 5 |
66MHz capable (otherwise 33MHz)
|
| 6 |
Device supports UDF
(user-definable features).
|
| 7 |
Capable of accepting fast back-to-back transactions
when the transactions are not to the same agent.
|
| 8 |
(bus masters only) Data parity error detected.
|
| 9-10 |
DEVSEL# encoding. 00=fast, 01=medium,
10=slow
|
| 11 |
Signaled Target Abort. This bit must be set by a target
when it terminates a transaction with Target-Abort.
|
| 12 |
Received Target Abort. This bit must be set by a
master device when its transaction is terminated by
a Target-Abort.
|
| 13 |
Received Master Abort. This bit must be set by a
master device whenever its transaction (except for
Special Cycle) is terminated with a Master-Abort.
|
| 14 |
Signaled System Error. This bit is set whenever the
device asserts SERR#.
|
| 15 |
Detected Parity Error. This bit is set when the device
detects a parity error, even if parity error handling
is disabled.
|
- Command Reg
- The contents (in hex) of the device's command register.
| Bit |
Meaning
|
| 0 |
IO Space. When set, allows the device to respond to
I/O Space accesses.
|
| 1 |
Memory Space. When set, allows the device to respond to
Memory Space accesses.
|
| 2 |
Bus Master. When set allows the device to behave as
a bus master.
|
| 3 |
Special Cycles. When set, allows the device to monitor
special cycle operations.
|
| 4 |
Memory Write and Invalidate Enable. When set, masters
may generate the Memory Write and Invalidate command.
When not set, the Memory Write command must be used
instead.
|
- Header type
- This byte identifies the layout of the device's configuration
space header and also indicates whether or not the device
contains multiple functions.
| Bit |
Meaning
|
| 0-6 |
These 7 bits identify the header layout. The
encoding 00h is the standard device header,
while the encoding 01h specifies the header
layout used for PCI-to-PCI bridges.
|
| 7 |
If set, this indicates a multi-function devices.
Otherwise, the device is a single-function device.
|
- BIST
- Built-in Self Test control and status (9 bit register). Devices that
do not support BIST will always return 0.
| Bit |
Meaning
|
| 7 |
BIST Capable. If set, the device supports BIST.
|
| 6 |
Start BIST. Software invoking BIST will write
a 1 to this bit location. The device
will reset to zero when the BIST
is complete.
|
| 5-4 |
Reserved. Always 0.
|
| 3-0 |
Completion code. A value of 0 means the device
passed the test. Non-zero values indicate failure.
Device-specific failure codes can be encoded into
the available 4 bits.
|
- Latency Timer
- This 8-bit value specifies (in units of PCI bus clocks) the
value of the latency timer for a PCI bus master device.
- Cache Line Size
- This 8-bit register specifies the system cacheline size (in
units of 32-bit words).
- Max Lat
- This value specifies the latency that the device will tolerate
in obtaining access to the PCI bus. The value is reported by
show_pci in nanoseconds.
- Min Gnt
- This value specifies how long a burst period the device needs
assuming a clock rate of 33MHz. This value is reported in
nanoseconds by the show_pci utility.
- PCI Int Pin
- This register specifies which interrupt pin the device uses:
| Value |
Meaning
|
| 1 |
INTA#
|
| 2 |
INTB#
|
| 3 |
INTC#
|
| 4 |
INTD#
|
Devices that do not use an interrupt pin will always put 0
in this register.
- Interrupt Line
- This is an 8-bit value used for interrupt line routing information.
The value in this register indicates which input of the system
interrupt controller(s) the device's interrupt pin is connected to.
The device itself does not use this value.
Show devices on the PCI bus:
show_pci
PCI Local Bus Specification, PCI Special
Interest Group, P.O. Box 14070 Portland, Oregon, USA 97214.
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