Information about each CPU chip in the system.
The system page's cpuinfo area contains information about each CPU chip in the system, such as the CPU type, speed, capabilities, performance, and cache sizes.
The number of instances of the cpuinfo_entry structure is equal to the number in the num_cpu member of the syspage_entry data structure (e.g., on a dual-processor system, there are two cpuinfo entries; on a four-processor system, four entries).
The cpuinfo_entry structure is automatically filled in by the startup library function init_cpuinfo(). Its members include:
The flags member contains a bitmapped indication of the capabilities of the CPU chip. The prefix for the manifest constant indicates the CPU family it applies to (e.g., ARM_ indicates that this constant is for use on the ARM family of processors). If there is no prefix the constant is generic; it is relevant to any CPU supported by QNX Neutrino RTOS.
The bits include the following:
This bit: | Means that the CPU has or supports: |
---|---|
CPU_FLAG_FPU | A Floating Point Unit (FPU) |
CPU_FLAG_MMU | A Memory Management Unit (MMU), and the MMU is enabled (i.e., the CPU is currently in virtual addressing mode) |
ARM_CPU_FLAG_CC_INCR_BIT_32 | A 32-bit clock cycle counter (CLOCKCYCLES_INCR_BIT is 32) |
ARM_CPU_FLAG_IDIV | H/W division: the UDIV and SDIV instructions are supported |
ARM_CPU_FLAG_LPAE | Large Physical Address Extension support is present and enabled |
ARM_CPU_FLAG_NEON | NEON technology, a 128-bit SIMD (Single Instruction, Multiple Data) architecture extension to the ARM Cortex-A series processor |
ARM_CPU_FLAG_SMP | Multiple processors |
ARM_CPU_FLAG_V7 | ARMv7 architecture |
ARM_CPU_FLAG_V7_MP | ARMv7 multiprocessor extensions |
ARM_CPU_FLAG_V7_MP_ERRATA | Needs SMP TLB workarounds |
ARM_CPU_FLAG_VFP_D32 | VFP has 32 double registers |
ARM_CPU_FLAG_WMMX2 | An iWMMX2 coprocessor |
ARM_CPU_FLAG_XSCALE_CP0 | Xscale CP0 MAC unit |
AARCH64_CPU_ACTLR | Auxiliary Control Register |
AARCH64_CPU_FLAG_SMP | Multiple processors |
AARCH64_CPU_FLAG_SIMD | NEON technology, a 128-bit SIMD (Single Instruction, Multiple Data) architecture extension to the ARM Cortex-A series processor |
AARCH64_CPU_FLAG_CC_INCR_32 | A 32-bit clock cycle counter (CLOCKCYCLES_INCR_BIT is 32) |
X86_CPU_AVX X86_64_CPU_AVX |
Advanced Vector Extensions |
X86_CPU_BSWAP X86_64_CPU_BSWAP |
BSWAP instruction |
X86_CPU_CMOV X86_64_CPU_CMOV |
CMOVxx instructions |
X86_CPU_CPUID X86_64_CPU_CPUID |
CPUID instruction |
X86_CPU_FXSR X86_64_CPU_FXSR |
FXSAVE/FXRSTOR instructions |
X86_CPU_INVARIANT_TSC X86_64_CPU_INVARIANT_TSC |
Invariant (constant) Time Stamp Counter |
X86_CPU_INVLPG X86_64_CPU_INVLPG |
INVLPG instruction |
X86_CPU_MMX X86_64_CPU_MMX |
MMX instructions |
X86_CPU_MTRR X86_64_CPU_MTRR |
MTRR (Memory Type Range Register) registers |
X86_CPU_NX X86_64_CPU_NX |
No-eXecute PTE bit |
X86_CPU_PAE X86_64_CPU_PAE |
Extended addressing |
X86_CPU_PAT X86_64_CPU_PAT |
Page Attribute Tables |
X86_CPU_PCID X86_64_CPU_PCID |
CPU supports Process-Context Identifiers |
X86_CPU_PGE X86_64_CPU_PGE |
TLB (Translation Lookaside Buffer) global mappings |
X86_CPU_PSE X86_64_CPU_PSE |
Needs TLB (Translation Lookaside Buffer) flush when splitting a large page |
X86_CPU_PTESPLIT_TLBFLUSH X86_64_CPU_PTESPLIT_TLBFLUSH |
Page size extensions |
X86_CPU_RDTSC X86_64_CPU_RDTSC |
RDTSC instruction |
X86_CPU_SEP X86_64_CPU_SEP |
SYSENTER and SYSEXIT instructions |
X86_CPU_SIMD X86_64_CPU_SIMD |
SIMD instructions |
X86_CPU_SSE2 X86_64_CPU_SSE2 |
Streaming SIMD Extensions 2 |
X86_CPU_XSAVE X86_64_CPU_XSAVE |
XSAVE and XRSTOR instructions |
X86_CPU_WP X86_64_CPU_WP |
WP bit in the CR0 register |